The trend in semiconductor memory arrays is toward increased areal density. Although a reduction in size provides some increase in areal density, other approaches may provide additional benefits. Three-dimensional (3D) crosspoint memory arrays allow for 3D stacked integration of memory cells. The stacking of memory cells results in a higher areal memory density. Each memory cell in such a 3D crosspoint memory array typically includes a memory element connected in series with a selection device. The memory element may be a magnetic tunneling junction or other resistive device. The selection device for such a memory cell is typically a transistor. The 3D crosspoint memory array also includes bit lines, word lines, and source lines. Bit lines are coupled to one end of the magnetic junctions, while the source lines are connected to the sources of the transistors. Word lines provide a selection voltage to the gates of the transistors. When the transistor is enabled, the selected memory cell may be written or read.
Although providing an additional avenue for increasing areal memory density, 3D stackable memory arrays have limitations. The 3D stackable memory arrays may have high power requirements for access. As such, the ability to integrate 3D stackable memories into certain technologies, such as system-on-a-chip (SoC) devices, may be limited. However, because of their potential for use increasing areal memory density, research in 3D stackable memories is ongoing.